1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a memory device for early stabilizing a power level after deep power down mode exit.
2. Description of the Related Art
In general, a semiconductor memory device has various operation modes including a standby mode, an active mode and a deep power down mode. In the standby mode, a chip enable signal /CE is at a logic high level and no chip is selected. In the active mode, commands are applied to the semiconductor memory device to enable read and write operations of the semiconductor memory. Internal power supply voltages in the standby mode are equal to those in the active mode. In the deep power down mode, the internal power supply voltages in the standby mode and the active mode are lowered to stop circuits operated by the internal power supply voltages and to lower current consumption to zero in an internal voltage generator including a boost circuit or a buck circuit.
FIG. 1 is a diagram for explaining the operation of a memory device when the operation mode of the memory device is changed from a deep power down (DPD) mode to a standby mode or to an active mode. Referring to FIG. 1, the memory device enters into the DPD mode when a DPD command signal is transitioned from a logic high level to a logic low level. The DPD mode lowers an internal power supply voltage of the device formerly operating in the standby mode or active mode to 0V.
When the DPD command signal is later changed from a logic low level to a logic high level, the memory device exits the DPD mode and the internal power supply voltage is boosted to a set level from 0V. The internal power supply voltage requires a certain period of time to be boosted to the set level from 0V. Accordingly, the memory device enters into the standby mode or the active mode after a lapse of power-up ensuring time after DPD mode exit.
FIG. 2 is a block diagram of a conventional memory device 200 that requires a power-up ensuring time after exiting the DPD mode. Referring to FIG. 2, the memory device 200 requires many different internal power supply voltages. These internal power supply voltages include a voltage used in a memory cell array block, a voltage used in a peripheral circuit, a voltage used in the DPD mode, a voltage used in the standby mode and a voltage used in the active mode.
The memory device 200 includes a circuit 210 for generating an internal voltage for the standby mode, a circuit 220 for generating an internal voltage for the active mode, a circuit 230 for generating an array internal voltage for the standby mode, a circuit 240 for generating an array internal voltage for the active mode, a circuit 250 for generating a high voltage for the standby mode, a circuit 260 for generating a high voltage for the active mode, and a DC bias circuit 270.
The circuits 210, 230 and 250 for generating the internal voltages for the standby mode respectively generate an internal power supply voltage VINT, an array internal power supply voltage VINTA and a high voltage VPP used in the standby mode in response to a DPD command DPD. The circuits 220, 240 and 260 for generating the internal voltages for the active mode respectively generate an internal power supply voltage VINT, an array internal power supply voltage VINTA and a high voltage VPP used in the active mode in response to an active command ACT.
The internal power supply voltage VINT, the array internal power supply voltage VINTA and the high voltage VPP used in the standby mode are respectively equal to the internal power supply voltage VINT, the array internal power supply voltage VINTA and the high voltage VPP used in the active mode. However, the quantities of the driving currents of the internal power supply voltage VINT, the array internal power supply voltage VINTA and the high voltage VPP used in the active mode are larger than those of the internal power supply voltage VINT, the array internal power supply voltage VINTA and the high voltage VPP used in the standby mode.
The internal power supply voltage VINT, the array internal power supply voltage VINTA and the high voltage VPP when the memory device exits the DPD mode have the current drivability of the internal power supply voltage VINT, the array internal power supply voltage VINTA and the high voltage VPP generated by the circuits 210, 230 and 250 for generating the internal voltages for the standby mode. Accordingly, the memory device 200 requires a time period for the internal power supply voltage VINT, the array internal power supply voltage VINTA and the high voltage VPP to have the current drivability applied to a suitable level in the active mode after DPD mode exit. For this reason, the memory device 200 requires the power-up ensuring time following the DPD mode exit, as illustrated in FIG. 1.
The power-up ensuring time after DPD mode exit is generally set to 200 μS by memory device specifications. This time is considerably long for systems including the memory device. Accordingly, a method of reducing the power-up ensuring time after DPD mode exit is required.